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ADP-N1 Adapter Board Data Sheet
(view source)
Revision as of 16:29, 15 July 2020
44 bytes removed
,
16:29, 15 July 2020
→Adapter Board Pinlist
Line 31:
Line 31:
|1
|1
|CAM_VSYNC
|CAM_VSYNC
−
|Internal Connect with
Pin86 of
J7 through a level shifter(1.8V to 3.3V)
+
|Internal Connect with J7
-86
through a level shifter(1.8V to 3.3V)
|-
|-
|2
|2
Line 39:
Line 39:
|3
|3
|Ext Trigger In
|Ext Trigger In
−
|Internal Connect with
Pin1 of
J9
+
|Internal Connect with J9
-1
|}
|}
{| class="wikitable"
{| class="wikitable"
Line 50:
Line 50:
|1
|1
|Ext Trigger In
|Ext Trigger In
−
|Internal Connect with
Pin3 of
J8
+
|Internal Connect with J8
-3
|-
|-
|2
|2
Line 67:
Line 67:
|-
|-
|Short connection J8-1 and J8-2
|Short connection J8-1 and J8-2
−
|Select
Pin86(CAM_VSYNC) of
J7 as the trigger source,Only available Interconnect with TX2 platform
+
|Select J7
-86(CAM_VSYNC)
as the trigger source,Only available Interconnect with TX2 platform
|-
|-
| rowspan="2" |Short connection J8-2 and J8-3
| rowspan="2" |Short connection J8-2 and J8-3
−
|Select
Pin1(Ext
Trigger
In) of J9
as the trigger source
+
|Select
J9-1(Ext
Trigger
In)
as the trigger source
|-
|-
−
|SW1 is used for testing to simulate an external trigger signal,Internal Connect with
Pin3 of
J9
+
|SW1 is used for testing to simulate an external trigger signal,Internal Connect with J9
-3
|}
|}
{| class="wikitable"
{| class="wikitable"
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