Difference between revisions of "Adapter Board for Rockchip"

From wiki_veye
Jump to navigation Jump to search
 
(30 intermediate revisions by 2 users not shown)
Line 1: Line 1:
−
[http://wiki.veye.cc/index.php/Adapter_Board for Rockchip/zh 查看中文]
+
[[Adapter Board for Rockchip/zh|查看中文]]
  
−
'''<big>Adapter Board for Rockchip Description</big>'''
+
'''<big><big><big>Adapter Board:ADP-RK Data Sheet</big></big></big>'''
  
−
===Introduction===
+
==Introduction==
 +
Adapter Board ADP-RK can be connected with the FriendlyARM Nano Pi M4,NEO4(RK3399)，Firefly-RK3399，NanoPi and AIO-3288C
  
−
===Adapter Board Diagram, Layout===
+
*Rockchip Board connect the NanoPi:
  
−
* J2 pin list
+
Connect J3 interface and CSI-2 interface on NanoPi with 0.5mm 30 pin pitch FFC cable(TypeA)[[File:VEYENanoPi&Firefly Adapter ROCK.jpg|thumb|483x483px|connector position（front）]][[File:VEYENanoPi&Firefly Adapter B .jpg|thumb|485x485px|connector position（back)]]
 +
==Adapter Board Diagram, Layout==
  
 
{| class="wikitable"
 
{| class="wikitable"
−
|+
+
| colspan="3" |'''J2'''
 +
|-
 +
|'''Pin NO.'''
 +
|'''NAME'''
 +
|'''Remarks'''
 +
|-
 
|1
 
|1
 
|GND
 
|GND
 +
|
 +
|-
 
|2
 
|2
 
|MIPI_L0_N
 
|MIPI_L0_N
 +
|
 
|-
 
|-
 
|3
 
|3
 
|MIPI_L0_P
 
|MIPI_L0_P
 +
|
 +
|-
 
|4
 
|4
 
|GND
 
|GND
 +
|
 
|-
 
|-
 
|5
 
|5
 
|MIPI_CK_N
 
|MIPI_CK_N
 +
|
 +
|-
 
|6
 
|6
 
|MIPI_CK_P
 
|MIPI_CK_P
 +
|
 
|-
 
|-
 
|7
 
|7
 
|GND
 
|GND
 +
|
 +
|-
 
|8
 
|8
−
|MIPI_L1_N
+
|MIPI_L1_1
 +
|
 
|-
 
|-
 
|9
 
|9
 
|MIPI_L1_P
 
|MIPI_L1_P
 +
|
 +
|-
 
|10
 
|10
 
|GND
 
|GND
 +
|
 
|-
 
|-
 
|11
 
|11
−
|MIPI_L2_N
+
|RESERVE
 +
|NC
 +
|-
 
|12
 
|12
−
|MIPI_L2_P
+
|RESERVE
 +
|NC
 
|-
 
|-
 
|13
 
|13
 
|GND
 
|GND
 +
|
 +
|-
 
|14
 
|14
−
|MIPI_L3_N
+
|RESERVE
 +
|NC
 
|-
 
|-
 
|15
 
|15
−
|MIPI_L3_P
+
|RESERVE
 +
|NC
 +
|-
 
|16
 
|16
 
|GND
 
|GND
 +
|
 
|-
 
|-
 
|17
 
|17
 
|MIPI_MCLK0
 
|MIPI_MCLK0
 +
|
 +
|-
 
|18
 
|18
 
|GND
 
|GND
 +
|
 
|-
 
|-
 
|19
 
|19
−
|GPIOx
+
|RESERVE
 +
|NC
 +
|-
 
|20
 
|20
−
|MIPI_RST
+
|RESERVE
 +
|NC
 
|-
 
|-
 
|21
 
|21
−
|MIPI_SCL_1V8
+
|SCL
 +
|1.8V Level
 +
|-
 
|22
 
|22
−
|MIPI_SDA_1V8
+
|SDA
 +
|1.8V Level
 
|-
 
|-
 
|23
 
|23
 
|GND
 
|GND
 +
|
 +
|-
 
|24
 
|24
−
|RESERVE, Not Connected
+
|RESERVE
 +
|NC
 
|-
 
|-
 
|25
 
|25
 
|GND
 
|GND
 +
|
 +
|-
 
|26
 
|26
 
|VCC5V
 
|VCC5V
 +
|PWR IN
 
|-
 
|-
 
|27
 
|27
−
|RESERVE, Not Connected
+
|RESERVE
 +
|NC
 +
|-
 
|28
 
|28
−
|RESERVE, Not Connected
+
|RESERVE
 +
|NC
 
|-
 
|-
 
|29
 
|29
−
|RESERVE, Not Connected
+
|RESERVE
 +
|NC
 +
|-
 
|30
 
|30
−
|RESERVE, Not Connected
+
|RESERVE
−
|}
+
|NC
−
 
+
|}  
−
* J3 pin list
 
−
 
 
 
{| class="wikitable"
 
{| class="wikitable"
−
|+
+
| colspan="3" |'''J3'''
 +
|-
 +
|'''Pin NO.'''
 +
|'''NAME'''
 +
|'''Remarks'''
 +
|-
 
|1
 
|1
 
|GND
 
|GND
 +
|
 +
|-
 
|2
 
|2
 
|MIPI_L0_N
 
|MIPI_L0_N
 +
|
 
|-
 
|-
 
|3
 
|3
 
|MIPI_L0_P
 
|MIPI_L0_P
 +
|
 +
|-
 
|4
 
|4
 
|GND
 
|GND
 +
|
 
|-
 
|-
 
|5
 
|5
 
|MIPI_CK_N
 
|MIPI_CK_N
 +
|
 +
|-
 
|6
 
|6
 
|MIPI_CK_P
 
|MIPI_CK_P
 +
|
 
|-
 
|-
 
|7
 
|7
 
|GND
 
|GND
 +
|
 +
|-
 
|8
 
|8
 
|MIPI_L1_N
 
|MIPI_L1_N
 +
|
 
|-
 
|-
 
|9
 
|9
 
|MIPI_L1_P
 
|MIPI_L1_P
 +
|
 +
|-
 
|10
 
|10
 
|GND
 
|GND
 +
|
 
|-
 
|-
 
|11
 
|11
−
|MIPI_L2_N
+
|RESERVE
 +
|NC
 +
|-
 
|12
 
|12
−
|MIPI_L2_P
+
|RESERVE
 +
|NC
 
|-
 
|-
 
|13
 
|13
 
|GND
 
|GND
 +
|
 +
|-
 
|14
 
|14
−
|MIPI_L3_N
+
|RESERVE
 +
|NC
 
|-
 
|-
 
|15
 
|15
−
|MIPI_L3_P
+
|RESERVE
 +
|NC
 +
|-
 
|16
 
|16
 
|GND
 
|GND
 +
|
 
|-
 
|-
 
|17
 
|17
 
|MIPI_MCLK0
 
|MIPI_MCLK0
 +
|
 +
|-
 
|18
 
|18
 
|GND
 
|GND
 +
|
 
|-
 
|-
 
|19
 
|19
−
|GPIOx
+
|RESERVE
 +
|NC
 +
|-
 
|20
 
|20
−
|MIPI_RST
+
|RESERVE
 +
|NC
 
|-
 
|-
 
|21
 
|21
−
|MIPI_SDA_1V8
+
|SDA
 +
|1.8V Level
 +
|-
 
|22
 
|22
−
|MIPI_SCL_1V8
+
|SCL
 +
|1.8V Level
 
|-
 
|-
 
|23
 
|23
−
|RESERVE, Not Connected
+
|RESERVE
 +
|NC
 +
|-
 
|24
 
|24
−
|RESERVE, Not Connected
+
|RESERVE
 +
|NC
 
|-
 
|-
 
|25
 
|25
−
|RESERVE, Not Connected
+
|RESERVE
 +
|NC
 +
|-
 
|26
 
|26
−
|RESERVE, Not Connected
+
|RESERVE
 +
|NC
 
|-
 
|-
 
|27
 
|27
−
|RESERVE, Not Connected
+
|RESERVE
 +
|NC
 +
|-
 
|28
 
|28
 
|GND
 
|GND
 +
|
 
|-
 
|-
 
|29
 
|29
−
|GND
+
|VCC5V
 +
|PWR IN
 +
|-
 
|30
 
|30
 
|VCC5V
 
|VCC5V
−
|}
+
|PWR IN
−
 
+
|}  
−
* J4 pin list
 
−
 
 
 
{| class="wikitable"
 
{| class="wikitable"
−
|+
+
| colspan="3" |'''J4'''
 +
|-
 +
|'''Pin NO.'''
 +
|'''NAME'''
 +
|'''Remarks'''
 +
|-
 
|1
 
|1
 
|MIPI_L0_N
 
|MIPI_L0_N
 +
|
 +
|-
 
|2
 
|2
 
|MIPI_L0_P
 
|MIPI_L0_P
 +
|
 
|-
 
|-
 
|3
 
|3
 
|GND
 
|GND
 +
|
 +
|-
 
|4
 
|4
 
|MIPI_L1_N
 
|MIPI_L1_N
 +
|
 
|-
 
|-
 
|5
 
|5
 
|MIPI_L1_P
 
|MIPI_L1_P
 +
|
 +
|-
 
|6
 
|6
 
|GND
 
|GND
 +
|
 
|-
 
|-
 
|7
 
|7
 
|MIPI_CK_N
 
|MIPI_CK_N
 +
|
 +
|-
 
|8
 
|8
 
|MIPI_CK_P
 
|MIPI_CK_P
 +
|
 
|-
 
|-
 
|9
 
|9
 
|GND
 
|GND
 +
|
 +
|-
 
|10
 
|10
−
|MIPI_L2_N
+
|RESERVE
 +
|NC
 
|-
 
|-
 
|11
 
|11
−
|MIPI_L2_P
+
|RESERVE
 +
|NC
 +
|-
 
|12
 
|12
 
|GND
 
|GND
 +
|
 
|-
 
|-
 
|13
 
|13
−
|MIPI_L3_N
+
|RESERVE
 +
|NC
 +
|-
 
|14
 
|14
−
|MIPI_L3_P
+
|RESERVE
 +
|NC
 
|-
 
|-
 
|15
 
|15
 
|GND
 
|GND
 +
|
 +
|-
 
|16
 
|16
 
|MIPI_MCLK0
 
|MIPI_MCLK0
 +
|
 
|-
 
|-
 
|17
 
|17
 
|GND
 
|GND
 +
|
 +
|-
 
|18
 
|18
−
|GPIOx
+
|RESERVE
 +
|NC
 
|-
 
|-
 
|19
 
|19
−
|MIPI_RST
+
|RESERVE
 +
|NC
 +
|-
 
|20
 
|20
−
|MIPI_SCL_1V8
+
|SCL
 +
|1.8V Level
 
|-
 
|-
 
|21
 
|21
−
|MIPI_SDA_1V8
+
|SDA
 +
|1.8V Level
 +
|-
 
|22
 
|22
 
|MIPI_PWR
 
|MIPI_PWR
 +
|
 
|-
 
|-
 
|23
 
|23
 
|CIF_PWR
 
|CIF_PWR
 +
|
 +
|-
 
|24
 
|24
 
|VCC5V
 
|VCC5V
 +
|
 +
|}
 +
{| class="wikitable"
 +
| colspan="6" |'''J1'''
 +
|-
 +
|'''Pin NO.'''
 +
|'''NAME'''
 +
|'''Remarks'''
 +
|'''Pin NO.'''
 +
|'''NAME'''
 +
|'''Remarks'''
 +
|-
 +
|1
 +
|RESERVE
 +
|NC
 +
|2
 +
|RESERVE
 +
|NC
 +
|-
 +
|3
 +
|GND
 +
|
 +
|4
 +
|RESERVE
 +
|NC
 +
|-
 +
|5
 +
|RESERVE
 +
|NC
 +
|6
 +
|RESERVE
 +
|NC
 +
|-
 +
|7
 +
|RESERVE
 +
|NC
 +
|8
 +
|RESERVE
 +
|NC
 +
|-
 +
|9
 +
|GND
 +
|
 +
|10
 +
|GND
 +
|
 +
|-
 +
|11
 +
|RESERVE
 +
|NC
 +
|12
 +
|RESERVE
 +
|NC
 +
|-
 +
|13
 +
|RESERVE
 +
|NC
 +
|14
 +
|RESERVE
 +
|NC
 +
|-
 +
|15
 +
|GND
 +
|
 +
|16
 +
|GND
 +
|
 +
|-
 +
|17
 +
|MIPI_CK_P
 +
|
 +
|18
 +
|SCL
 +
|3.3V Level
 +
|-
 +
|19
 +
|MIPI_CK_N
 +
|
 +
|20
 +
|SDA
 +
|3.3V Level
 +
|-
 +
|21
 +
|GND
 +
|
 +
|22
 +
|RESERVE
 +
|NC
 +
|-
 +
|23
 +
|MIPI_L1_P
 +
|
 +
|24
 +
|RESERVE
 +
|NC
 +
|-
 +
|25
 +
|MIPI_L1_N
 +
|
 +
|26
 +
|RESERVE
 +
|NC
 +
|-
 +
|27
 +
|GND
 +
|
 +
|28
 +
|RESERVE
 +
|NC
 +
|-
 +
|29
 +
|MIPI_L0_P
 +
|
 +
|30
 +
|RESERVE
 +
|NC
 +
|-
 +
|31
 +
|MIPI_L0_N
 +
|
 +
|32
 +
|RESERVE
 +
|NC
 +
|-
 +
|33
 +
|GND
 +
|
 +
|34
 +
|GND
 +
|
 +
|-
 +
|35
 +
|GND
 +
|
 +
|36
 +
|GND
 +
|
 +
|-
 +
|37
 +
|VCC3V3
 +
|
 +
|38
 +
|VCC3V3
 +
|
 +
|-
 +
|39
 +
|VCC3V3
 +
|
 +
|40
 +
|VCC3V3
 +
|
 
|}
 
|}
 +
 +
==Board Dimension==
 +
[[File:ADP-RK结构图纸.jpg|thumb|600x600px|CS-MIPI-IMX307 CAD drawing / unit : mm|alt=|none]]
 +
[[Media:ADP-RK CAD.dwg|Download dwg file here]]

Latest revision as of 19:54, 9 July 2020

查看中文

Adapter Board:ADP-RK Data Sheet

1 Introduction

Adapter Board ADP-RK can be connected with the FriendlyARM Nano Pi M4,NEO4(RK3399)，Firefly-RK3399，NanoPi and AIO-3288C

  • Rockchip Board connect the NanoPi:

Connect J3 interface and CSI-2 interface on NanoPi with 0.5mm 30 pin pitch FFC cable(TypeA)

connector position（front）
connector position（back)

2 Adapter Board Diagram, Layout

J2
Pin NO. NAME Remarks
1 GND
2 MIPI_L0_N
3 MIPI_L0_P
4 GND
5 MIPI_CK_N
6 MIPI_CK_P
7 GND
8 MIPI_L1_1
9 MIPI_L1_P
10 GND
11 RESERVE NC
12 RESERVE NC
13 GND
14 RESERVE NC
15 RESERVE NC
16 GND
17 MIPI_MCLK0
18 GND
19 RESERVE NC
20 RESERVE NC
21 SCL 1.8V Level
22 SDA 1.8V Level
23 GND
24 RESERVE NC
25 GND
26 VCC5V PWR IN
27 RESERVE NC
28 RESERVE NC
29 RESERVE NC
30 RESERVE NC
J3
Pin NO. NAME Remarks
1 GND
2 MIPI_L0_N
3 MIPI_L0_P
4 GND
5 MIPI_CK_N
6 MIPI_CK_P
7 GND
8 MIPI_L1_N
9 MIPI_L1_P
10 GND
11 RESERVE NC
12 RESERVE NC
13 GND
14 RESERVE NC
15 RESERVE NC
16 GND
17 MIPI_MCLK0
18 GND
19 RESERVE NC
20 RESERVE NC
21 SDA 1.8V Level
22 SCL 1.8V Level
23 RESERVE NC
24 RESERVE NC
25 RESERVE NC
26 RESERVE NC
27 RESERVE NC
28 GND
29 VCC5V PWR IN
30 VCC5V PWR IN
J4
Pin NO. NAME Remarks
1 MIPI_L0_N
2 MIPI_L0_P
3 GND
4 MIPI_L1_N
5 MIPI_L1_P
6 GND
7 MIPI_CK_N
8 MIPI_CK_P
9 GND
10 RESERVE NC
11 RESERVE NC
12 GND
13 RESERVE NC
14 RESERVE NC
15 GND
16 MIPI_MCLK0
17 GND
18 RESERVE NC
19 RESERVE NC
20 SCL 1.8V Level
21 SDA 1.8V Level
22 MIPI_PWR
23 CIF_PWR
24 VCC5V
J1
Pin NO. NAME Remarks Pin NO. NAME Remarks
1 RESERVE NC 2 RESERVE NC
3 GND 4 RESERVE NC
5 RESERVE NC 6 RESERVE NC
7 RESERVE NC 8 RESERVE NC
9 GND 10 GND
11 RESERVE NC 12 RESERVE NC
13 RESERVE NC 14 RESERVE NC
15 GND 16 GND
17 MIPI_CK_P 18 SCL 3.3V Level
19 MIPI_CK_N 20 SDA 3.3V Level
21 GND 22 RESERVE NC
23 MIPI_L1_P 24 RESERVE NC
25 MIPI_L1_N 26 RESERVE NC
27 GND 28 RESERVE NC
29 MIPI_L0_P 30 RESERVE NC
31 MIPI_L0_N 32 RESERVE NC
33 GND 34 GND
35 GND 36 GND
37 VCC3V3 38 VCC3V3
39 VCC3V3 40 VCC3V3

3 Board Dimension

CS-MIPI-IMX307 CAD drawing / unit : mm

Download dwg file here

Retrieved from "http://wiki.veye.cc/index.php?title=Adapter_Board_for_Rockchip&oldid=2771"