Difference between revisions of "Adapter Board for Raspberry Pi"
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===Enhance Board Diagram, Layout=== | ===Enhance Board Diagram, Layout=== | ||
− | *J9 pin list | + | *'''J9 pin list''' |
{| class="wikitable" | {| class="wikitable" | ||
Line 64: | Line 64: | ||
|} | |} | ||
− | *J2 pin list | + | *[[File:VeyeRaspberryPi Ultra B .jpg|thumb|484x484px]]'''J2 pin list''' |
{| class="wikitable" | {| class="wikitable" | ||
Line 109: | Line 109: | ||
|} | |} | ||
− | *J4 pin list | + | *'''J4 pin list''' |
{| class="wikitable" | {| class="wikitable" | ||
Line 118: | Line 118: | ||
|2 | |2 | ||
|GND | |GND | ||
+ | |} | ||
+ | |||
+ | * '''J1 pin list''' | ||
+ | |||
+ | {| class="wikitable" | ||
+ | |1 | ||
+ | |RESERVE, Not Connected | ||
+ | |2 | ||
+ | |RESERVE, Not Connected | ||
+ | |- | ||
+ | |3 | ||
+ | |GND | ||
+ | |4 | ||
+ | |RESERVE, Not Connected | ||
+ | |- | ||
+ | |5 | ||
+ | |MIPI_L3_P | ||
+ | |6 | ||
+ | |RESERVE, Not Connected | ||
+ | |- | ||
+ | |7 | ||
+ | |MIPI_L3_N | ||
+ | |8 | ||
+ | |RESERVE, Not Connected | ||
+ | |- | ||
+ | |9 | ||
+ | |GND | ||
+ | |10 | ||
+ | |GND | ||
+ | |- | ||
+ | |11 | ||
+ | |MIPI_L2_P | ||
+ | |12 | ||
+ | |RESERVE, Not Connected | ||
+ | |- | ||
+ | |13 | ||
+ | |MIPI_L2_N | ||
+ | |14 | ||
+ | |RESERVE, Not Connected | ||
+ | |- | ||
+ | |15 | ||
+ | |GND | ||
+ | |16 | ||
+ | |GND | ||
+ | |- | ||
+ | |17 | ||
+ | |MIPI_CK_P | ||
+ | |18 | ||
+ | |SCL_3.3V | ||
+ | |- | ||
+ | |19 | ||
+ | |MIPI_CK_N | ||
+ | |20 | ||
+ | |SDA_3.3V | ||
+ | |- | ||
+ | |21 | ||
+ | |GND | ||
+ | |22 | ||
+ | |RESERVE, Not Connected | ||
+ | |- | ||
+ | |23 | ||
+ | |MIPI_L1_P | ||
+ | |24 | ||
+ | |RESERVE, Not Connected | ||
+ | |- | ||
+ | |25 | ||
+ | |MIPI_L1_N | ||
+ | |26 | ||
+ | |RESERVE, Not Connected | ||
+ | |- | ||
+ | |27 | ||
+ | |GND | ||
+ | |28 | ||
+ | |RESERVE, Not Connected | ||
+ | |- | ||
+ | |29 | ||
+ | |MIPI_L0_P | ||
+ | |30 | ||
+ | |RESERVE, Not Connected | ||
+ | |- | ||
+ | |31 | ||
+ | |MIPI_L0_N | ||
+ | |32 | ||
+ | |RESERVE, Not Connected | ||
+ | |- | ||
+ | |33 | ||
+ | |GND | ||
+ | |34 | ||
+ | |GND | ||
+ | |- | ||
+ | |35 | ||
+ | |GND | ||
+ | |36 | ||
+ | |GND | ||
+ | |- | ||
+ | |37 | ||
+ | |VCC3V3 | ||
+ | |38 | ||
+ | |VCC3V3 | ||
+ | |- | ||
+ | |39 | ||
+ | |VCC3V3 | ||
+ | |40 | ||
+ | |VCC3V3 | ||
|} | |} |
Revision as of 11:54, 24 July 2019
Enhance Board Diagram, Layout
- J9 pin list
1 | MIPI_L0_N | 2 | MIPI_L0_P |
3 | GND | 4 | MIPI_L1_N |
5 | MIPI_L1_P | 6 | GND |
7 | MIPI_CK_N | 8 | MIPI_CK_P |
9 | GND | 10 | CN |
11 | CN | 12 | GND |
13 | CN | 14 | CN |
15 | GND | 16 | ENABLE |
17 | RST_TEST | 18 | GND |
19 | Triggerln_SCL | 20 | TriggerOut_SDA |
21 | CN | 22 | GND |
- J2 pin list
1 | MIPI_L0_N | 2 | MIPI_L0_P |
3 | GND | 4 | MIPI_L1_N |
5 | MIPI_L1_P | 6 | GND |
7 | MIPI_CK_N | 8 | MIPI_CK_P |
9 | GND | 10 | ENABLE |
11 | RST_TEST | 12 | Triggerln_SCL |
13 | TriggerOut_SDA | 14 | CN |
15 | GND |
- J4 pin list
1 | +5V |
2 | GND |
- J1 pin list
1 | RESERVE, Not Connected | 2 | RESERVE, Not Connected |
3 | GND | 4 | RESERVE, Not Connected |
5 | MIPI_L3_P | 6 | RESERVE, Not Connected |
7 | MIPI_L3_N | 8 | RESERVE, Not Connected |
9 | GND | 10 | GND |
11 | MIPI_L2_P | 12 | RESERVE, Not Connected |
13 | MIPI_L2_N | 14 | RESERVE, Not Connected |
15 | GND | 16 | GND |
17 | MIPI_CK_P | 18 | SCL_3.3V |
19 | MIPI_CK_N | 20 | SDA_3.3V |
21 | GND | 22 | RESERVE, Not Connected |
23 | MIPI_L1_P | 24 | RESERVE, Not Connected |
25 | MIPI_L1_N | 26 | RESERVE, Not Connected |
27 | GND | 28 | RESERVE, Not Connected |
29 | MIPI_L0_P | 30 | RESERVE, Not Connected |
31 | MIPI_L0_N | 32 | RESERVE, Not Connected |
33 | GND | 34 | GND |
35 | GND | 36 | GND |
37 | VCC3V3 | 38 | VCC3V3 |
39 | VCC3V3 | 40 | VCC3V3 |