Difference between revisions of "FPD-LINK3-TX Data Sheet index"

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<big><big><big>'''FPD-LINK3-TX Data Sheet （FPD-LINK3-TX数据手册）'''</big></big></big>
 
<big><big><big>'''FPD-LINK3-TX Data Sheet （FPD-LINK3-TX数据手册）'''</big></big></big>
−
 
−
==Product Introduction（产品介绍）==
 
  
 
==Product Picture（产品图片）==
 
==Product Picture（产品图片）==
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|[[File:FPD-LINK3-TX 01.jpg|alt=|center|thumb|200x200px]]
 
|[[File:FPD-LINK3-TX 01.jpg|alt=|center|thumb|200x200px]]
 
|[[File:FPD-LINK3-TX 02.jpg|alt=|center|thumb|200x200px]]
 
|[[File:FPD-LINK3-TX 02.jpg|alt=|center|thumb|200x200px]]
 +
|}
 +
 +
== Thechnical Detail (技术规格) ==
 +
{| class="wikitable"
 +
| colspan="2" |'''Thechnical Detail (技术规格)'''
 +
|-
 +
| colspan="2" |'''2 MP MIPI® CSI-2 FPD-Link III serializer'''
 +
|-
 +
|IC PART NO.
 +
|[https://www.ti.com/product/DS90UB953-Q1 DS90UB953-Q1] / [https://www.ti.com/product/TSER953 TSER953RHBT]
 +
|-
 +
|Function
 +
|Serializer
 +
|-
 +
|Input Compatibility
 +
|MIPI CSI-2
 +
|-
 +
|Output Compatibility
 +
|[https://www.ti.com/interface/high-speed-serdes/fpd-link-serdes/overview.html FPD-Link III LVDS] / [https://www.ti.com/interface/high-speed-serdes/v3link-serdes/overview.html V3Link SerDes]
 +
|-
 +
|'''Interface'''
 +
|
 +
|-
 +
|MIPI INPUT
 +
|MIPI CSI-2 2lane (800Mbsp/lane max), J5 J6 Support
 +
MIPI CSI-2 4lane (800Mbsp/lane max), J3 Support
 +
|-
 +
|MIPI INPUT Connector
 +
|FFC socket（J3 J5），B2B Connector（J6）
 +
|-
 +
|LVDS OUTPUT
 +
|FPD-Link III LVDS (4Gbps data rate)
 +
|-
 +
|LVDS OUTPUT Connector
 +
|FAKRA Z Compatibility
 +
|-
 +
|MPIO
 +
|Up to 4 Multi-function IO
 +
|-
 +
| colspan="2" |'''Device Functional Modes'''
 +
|-
 +
|Clocking Mode
 +
|Synchronous Mode， FPD-Link III Clock reference derived from deserializer
 +
|-
 +
|FPD-Link III Operating Mode
 +
|CSI-2 Mode
 +
|-
 +
|Forward Channel Mode
 +
|Synchronous Mode
 +
|-
 +
|Back Channel Mode
 +
|Synchronous Mode
 +
|-
 +
|FPD-Link Line Rate
 +
|4.0 Gbps （Link with [[FPD-LINK3-2RX Data Sheet index|FPD-LINK3-2RX]]）
 +
|-
 +
|Back Channel Rate
 +
|50 Mbps （Link with [[FPD-LINK3-2RX Data Sheet index|FPD-LINK3-2RX]]）
 +
|-
 +
| colspan="2" |'''General'''
 +
|-
 +
|Operating Conditions
 +
('''Bare PCB''')
 +
|Operating guarantee temperature：'''-20℃~85℃''', Humidity 95% or less, non-condensing
 +
|-
 +
|POC DC Power Input
 +
|DC 9-15V （J2）
 +
|-
 +
|Dimension
 +
|38mm*38mm
 
|}
 
|}
 
[[File:FPD-LINK3-TX 03 IF.jpg|alt=|thumb|600x600px|FPD-LINK3-TX Pin List]]
 
[[File:FPD-LINK3-TX 03 IF.jpg|alt=|thumb|600x600px|FPD-LINK3-TX Pin List]]
 
[[File:FPD-LINK3-TX 04 IF.jpg|alt=|thumb|600x600px|FPD-LINK3-TX Pin List]]
 
[[File:FPD-LINK3-TX 04 IF.jpg|alt=|thumb|600x600px|FPD-LINK3-TX Pin List]]
 +
[[File:FPD LINK III-TX PIN.png|alt=|thumb|600x600px|FPD-LINK3-TX Pin]]
  
−
==Adapter Board Pinlist（接口和引脚说明）==
+
==Board Pinlist（接口和引脚说明）==
 
{| class="wikitable"
 
{| class="wikitable"
−
| colspan="3" |'''J1'''
+
| colspan="3" |'''J1:'''
 +
'''Connect to CS-MIPI-SC132's J7'''
 +
 
 +
'''Connect to CS-MIPI-IMX307's J7'''
 
|-
 
|-
 
|'''<small>Pin NO.（引脚号）</small>'''
 
|'''<small>Pin NO.（引脚号）</small>'''
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|-
 
|-
 
|1
 
|1
−
|GPIO0
+
|MPIO0
−
|
+
|3.3V Level
 
|-
 
|-
 
|2
 
|2
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|-
 
|-
 
|3
 
|3
−
|GPIO1
+
|MPIO1
−
|
+
|3.3V Level
 
|}
 
|}
 
{| class="wikitable"
 
{| class="wikitable"
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|-
 
|-
 
|1
 
|1
−
|GPIO2
+
|MPIO2
−
|
+
|3.3V Level
 
|-
 
|-
 
|2
 
|2
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|-
 
|-
 
|3
 
|3
−
|GPIO3
+
|MPIO3
−
|
+
|3.3V Level
 
|}
 
|}
 
{| class="wikitable"
 
{| class="wikitable"
−
| colspan="3" |'''J4: POC interface'''
+
| colspan="2" |'''J2'''：'''POC interface（POC接口）'''
 +
|-
 +
|'''Connector（接插件）'''
 +
|'''Interface Definition（接口定义）'''
 +
|-
 +
|FAKRA Z
 +
|[[File:Polarity diagram.png|center|thumb|200x200px|alt=|'''+：POC signal  /  -：GND''']]
 
|}
 
|}
 
{| class="wikitable"
 
{| class="wikitable"
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|1
 
|1
 
|VCC3V3
 
|VCC3V3
−
|PWR
+
|PWR OUT
 
|2
 
|2
 
|VCC3V3
 
|VCC3V3
−
|PWR
+
|PWR OUT
 
|-
 
|-
 
|3
 
|3
 
| VCC3V3
 
| VCC3V3
−
|PWR
+
|PWR OUT
 
|4
 
|4
 
|VCC3V3
 
|VCC3V3
−
|PWR
+
|PWR OUT
 
|-
 
|-
 
|5
 
|5
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|2
 
|2
 
|VCC3V3
 
|VCC3V3
−
|PWR IN
+
|PWR OUT
 
|-
 
|-
 
|3
 
|3
 
|VCC3V3
 
|VCC3V3
−
|PWR IN
+
|PWR OUT
 
|-
 
|-
 
|4
 
|4
 
|VCC3V3
 
|VCC3V3
−
|PWR IN
+
|PWR OUT
 
|-
 
|-
 
|5
 
|5
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|11
 
|11
 
|MPIO1
 
|MPIO1
−
|
+
|3.3V Level
 
|-
 
|-
 
|12
 
|12
 
|MPIO0
 
|MPIO0
−
|
+
|3.3V Level
 
|-
 
|-
 
|13
 
|13
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==Board Dimension（板子尺寸）==
 
==Board Dimension（板子尺寸）==
−
__FORCETOC__
+
[[File:FPDLINK3-TX JPG DWG.jpg|alt=|none|thumb|600x600px|FPD-LINK3-TX CAD / unit:mm]]
 +
[[Media:FPDLINK3-TX DWG.dwg|Download dwg file here]]
 +
== PCBA 3D STP File ==
 +
[[Media:3D FPD-LINK3-TX.zip|download 3D STP file]]

Latest revision as of 11:22, 9 October 2022

FPD-LINK3-TX Data Sheet （FPD-LINK3-TX数据手册）

1 Product Picture（产品图片）

PART NUMBER / 型号 FRONT VIEW / 正面图片 BACK VIEW / 背面图片
FPD-LINK3-TX

2 Thechnical Detail (技术规格)

Thechnical Detail (技术规格)
2 MP MIPI® CSI-2 FPD-Link III serializer
IC PART NO. DS90UB953-Q1 / TSER953RHBT
Function Serializer
Input Compatibility MIPI CSI-2
Output Compatibility FPD-Link III LVDS / V3Link SerDes
Interface
MIPI INPUT MIPI CSI-2 2lane (800Mbsp/lane max), J5 J6 Support

MIPI CSI-2 4lane (800Mbsp/lane max), J3 Support

MIPI INPUT Connector FFC socket（J3 J5），B2B Connector（J6）
LVDS OUTPUT FPD-Link III LVDS (4Gbps data rate)
LVDS OUTPUT Connector FAKRA Z Compatibility
MPIO Up to 4 Multi-function IO
Device Functional Modes
Clocking Mode Synchronous Mode， FPD-Link III Clock reference derived from deserializer
FPD-Link III Operating Mode CSI-2 Mode
Forward Channel Mode Synchronous Mode
Back Channel Mode Synchronous Mode
FPD-Link Line Rate 4.0 Gbps （Link with FPD-LINK3-2RX）
Back Channel Rate 50 Mbps （Link with FPD-LINK3-2RX）
General
Operating Conditions

(Bare PCB)

Operating guarantee temperature：-20℃~85℃, Humidity 95% or less, non-condensing
POC DC Power Input DC 9-15V （J2）
Dimension 38mm*38mm
FPD-LINK3-TX Pin List
FPD-LINK3-TX Pin List
FPD-LINK3-TX Pin

3 Board Pinlist（接口和引脚说明）

J1:

Connect to CS-MIPI-SC132's J7

Connect to CS-MIPI-IMX307's J7

Pin NO.（引脚号） NAME（名称） Remarks（说明）
1 MPIO0 3.3V Level
2 GND
3 MPIO1 3.3V Level
J4
Pin NO.（引脚号） NAME（名称） Remarks（说明）
1 MPIO2 3.3V Level
2 GND
3 MPIO3 3.3V Level
J2：POC interface（POC接口）
Connector（接插件） Interface Definition（接口定义）
FAKRA Z
+：POC signal / -：GND
J5 : Connect to CS-MIPI-IMX307's J8 （与CS-MIPI-IMX307 J8互联）
Pin NO.（引脚号） NAME（名称） Remarks（说明）
1 GND
2 MIPI_L0_N
3 MIPI_L0_P
4 GND
5 MIPI_L1_N
6 MIPI_L1_P
7 GND
8 MIPI_CK_N
9 MIPI_CK_P
10 GND
11 RESERVE NC
12 RESERVE NC
13 SCL 3.3V Level
14 SDA 3.3V Level
15 VCC3V3 PWR OUT
J6：Connect to VEYE-MIPI-327's J5 （与VEYE-MIPI-327 J5互联）
Pin NO.（引脚号） NAME（名称） Remarks（说明） Pin NO.（引脚号） NAME（名称） Remarks（说明）
1 VCC3V3 PWR OUT 2 VCC3V3 PWR OUT
3 VCC3V3 PWR OUT 4 VCC3V3 PWR OUT
5 GND 6 GND
7 GND 8 GND
9 MIPI_L0_N 10 NC
11 MIPI_L0_P 12 NC
13 GND 14 NC
15 MIPI_L1_N 16 NC
17 MIPI_L1_P 18 NC
19 GND 20 NC
21 MIPI_CK_N 22 SDA 3.3V LEVEL
23 MIPI_CK_P 24 SCL 3.3V LEVEL
25 GND 26 GND
27 NC 28 NC
29 NC 30 NC
31 GND 32 GND
33 NC 34 NC
35 NC 36 NC
37 GND 38 NC
39 NC 40 NC
J3: RESERVE （预留）
Pin NO.（引脚号） NAME（名称） Remarks（说明）
1 GND
2 VCC3V3 PWR OUT
3 VCC3V3 PWR OUT
4 VCC3V3 PWR OUT
5 MPIO3
6 MPIO2
7 GND
8 SDA 3.3V LEVEL
9 SCL 3.3V LEVEL
10 GND
11 MPIO1 3.3V Level
12 MPIO0 3.3V Level
13 GND
14 MIPI_L0_N
15 MIPI_L0_P
16 GND
17 MIPI_L1_N
18 MIPI_L1_P
19 GND
20 MIPI_CK_N
21 MIPI_CK_P
22 GND
23 MIPI_L2_N
24 MIPI_L2_P
25 GND
26 MIPI_L3_N
27 MIPI_L3_P
28 GND

4 Board Dimension（板子尺寸）

FPD-LINK3-TX CAD / unit:mm

Download dwg file here

5 PCBA 3D STP File

download 3D STP file

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