Difference between revisions of "LVDS时序和数据格式"
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{| class="wikitable" | {| class="wikitable" | ||
− | | colspan="17 | + | | colspan="17" |'''LVDS TIMING''' |
|- | |- | ||
− | | | + | |'''LVDS BUS''' |
− | + | | colspan="2" |'''Dn-1''' | |
− | | colspan="2" | | + | | colspan="7" |'''Dn''' |
− | | colspan="7" | | + | | colspan="5" |'''Dn+1''' |
− | | colspan="5" | | + | | |
− | | | + | |'''Parallel Data''' |
− | | | ||
|- | |- | ||
|CLK | |CLK | ||
Line 81: | Line 80: | ||
|… | |… | ||
|<--C[0:6] | |<--C[0:6] | ||
+ | |} | ||
+ | {| class="wikitable" | ||
+ | | colspan="17" |'''YUV TIMING''' | ||
|- | |- | ||
− | | | + | |'''LVDS BUS''' |
− | + | | colspan="2" |'''Dn-1''' | |
− | + | | colspan="7" |'''Dn''' | |
− | + | | colspan="5" |'''Dn+1''' | |
− | | colspan="2" | | + | | |
− | | colspan="7" | | + | |'''YUV Parallel Data''' |
− | | colspan="5" | | ||
− | | | ||
− | | | ||
|- | |- | ||
|CLK | |CLK | ||
Line 165: | Line 164: | ||
|} | |} | ||
{| class="wikitable" | {| class="wikitable" | ||
− | | | + | |'''Lane NO.''' |
− | | | + | |'''Interface''' |
− | | | + | |'''YUV Data''' |
− | | | + | |'''Xilinx SelectIO Parallel Data Output''' |
− | |||
|- | |- | ||
− | | rowspan="7" |L0 | + | | rowspan="7" |'''L0''' |
|A6 | |A6 | ||
|UNUSE | |UNUSE | ||
Line 200: | Line 198: | ||
|lvds_data_out[0] | |lvds_data_out[0] | ||
|- | |- | ||
− | | rowspan="7" |L1 | + | | rowspan="7" |'''L1''' |
|B6 | |B6 | ||
|Y3 | |Y3 | ||
Line 229: | Line 227: | ||
|lvds_data_out[1] | |lvds_data_out[1] | ||
|- | |- | ||
− | | rowspan="7" |L2 | + | | rowspan="7" |'''L2''' |
|C6 | |C6 | ||
|UV2 | |UV2 |
Revision as of 11:00, 6 December 2021
LVDS TIMING | ||||||||||||||||
LVDS BUS | Dn-1 | Dn | Dn+1 | Parallel Data | ||||||||||||
CLK | ▔ | ▔ | ▔ | ▔ | ▁ | ▁ | ▁ | ▔ | ▔ | ▔ | ▔ | ▁ | ▁ | ▁ | ||
LANE0 | A5 | A6 | A0 | A1 | A2 | A3 | A4 | A5 | A6 | A0 | A1 | A2 | A3 | A4 | … | <--A[0:6] |
LANE1 | B5 | B6 | B0 | B1 | B2 | B3 | B4 | B5 | B6 | B0 | B1 | B2 | B3 | B4 | … | <--B[0:6] |
LANE2 | C5 | C6 | C0 | C1 | C2 | C3 | C4 | C5 | C6 | C0 | C1 | C2 | C3 | C4 | … | <--C[0:6] |
YUV TIMING | ||||||||||||||||
LVDS BUS | Dn-1 | Dn | Dn+1 | YUV Parallel Data | ||||||||||||
CLK | ▔ | ▔ | ▔ | ▔ | ▁ | ▁ | ▁ | ▔ | ▔ | ▔ | ▔ | ▁ | ▁ | ▁ | ||
LANE0 | XX | XX | Y2 | Y1 | Y0 | FV | LV | 0 | 0 | Y2 | Y1 | Y0 | FV | LV | … | <--A[0:6] |
LANE1 | Y4 | Y3 | UV1 | UV0 | Y7 | Y6 | Y5 | Y4 | Y3 | UV1 | UV0 | Y7 | Y6 | Y5 | … | <--B[0:6] |
LANE2 | UV3 | UV2 | DE | UV7 | UV6 | UV5 | UV4 | UV3 | UV2 | DE | UV7 | UV6 | UV5 | UV4 | … | <--C[0:6] |
Lane NO. | Interface | YUV Data | Xilinx SelectIO Parallel Data Output |
L0 | A6 | UNUSE | lvds_data_out[18] |
A5 | UNUSE | lvds_data_out[15] | |
A4 | LV | lvds_data_out[12] | |
A3 | FV | lvds_data_out[9] | |
A2 | Y0 | lvds_data_out[6] | |
A1 | Y1 | lvds_data_out[3] | |
A0 | Y2 | lvds_data_out[0] | |
L1 | B6 | Y3 | lvds_data_out[19] |
B5 | Y4 | lvds_data_out[16] | |
B4 | Y5 | lvds_data_out[13] | |
B3 | Y6 | lvds_data_out[10] | |
B2 | Y7 | lvds_data_out[7] | |
B1 | UV0 | lvds_data_out[4] | |
B0 | UV1 | lvds_data_out[1] | |
L2 | C6 | UV2 | lvds_data_out[20] |
C5 | UV3 | lvds_data_out[17] | |
C4 | UV4 | lvds_data_out[14] | |
C3 | UV5 | lvds_data_out[11] | |
C2 | UV6 | lvds_data_out[8] | |
C1 | UV7 | lvds_data_out[5] | |
C0 | DE | lvds_data_out[2] |