Difference between revisions of "ADP-N4 Adapter Board Data Sheet"

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Line 1: Line 1:
<big><big><big>'''Adapter Board:ADP-N1-V2.0 Data Sheet'''</big></big></big>
+
<big><big><big>'''Adapter Board:ADP-N4 Data Sheet'''</big></big></big>
  
 
==Product Introduction(产品介绍)==
 
==Product Introduction(产品介绍)==
ADP-N1-V2.0 is a camera interposer module for NVIDIA Jetson AGX Xavier & TX2 DevKit.  
+
ADP-N4 is a camera interposer module for NVIDIA Jetson AGX Xavier、ORIN 、TX2 DevKit.  
  
ADP-N1-V2.0 is an upgrade of ADP-N1,added external 12V power supply function.
+
ADP-N1-V2.0是NVIDIA Jetson AGX Xavier、ORIN、TX2开发套件的摄像头转接模块。
 
 
When 12V power supply is used, 3.3V power supply of the main board will be automatically cut off.
 
 
 
ADP-N1-V2.0是NVIDIA Jetson AGX Xavier和TX2开发套件的摄像头转接模块。
 
 
 
ADP-N1-V2.0是ADP-N1的升级款,增加了外部12V供电功能。
 
 
 
当使用12V供电时,自动切断主板3.3V供电。
 
  
 
==Product Picture(产品图片)==
 
==Product Picture(产品图片)==
Line 19: Line 11:
 
|'''FRONT VIEW / 正面图片'''
 
|'''FRONT VIEW / 正面图片'''
 
|'''BACK VIEW / 背面图片'''
 
|'''BACK VIEW / 背面图片'''
|'''FFC CABLE/FFC线缆'''
 
 
|-
 
|-
|'''ADP-N1'''
+
|'''ADP-N4'''
|[[File:ADP-N1-V2.0 001.jpg|alt=|center|thumb|200x200px|'''ADP-N1-V2.0''']]
+
|[[File:ADP-N4 01.jpg|alt=|center|thumb|200x200px|'''ADP-N4''']]
|[[File:ADP-N1-V2.0 002.jpg|alt=|center|thumb|200x200px|'''ADP-N1-V2.0''']]
+
|[[File:ADP-N4 02.jpg|alt=|center|thumb|200x200px|'''ADP-N4''']]
|[[File:FFC30-0.5-KH.jpg|alt=|center|thumb|200x200px|'''FFC28P-0.5MM-20CM-T''']]
 
 
|}
 
|}
[[File:ADP-N1-V2.0 005.jpg|alt=|thumb|600x600px|ADP-N1-V2.0 pinlist]]
+
[[File:ADP-N4 04.jpg|alt=|thumb|600x600px|ADP-N4]]
[[File:ADP-N1-V2.0 006.jpg|alt=|thumb|600x600px|ADP-N1-V2.0 pinlist]]
+
[[File:ADP-N4 03.jpg|alt=|thumb|600x600px|ADP-N4]]
  
 
==Adapter Board Pinlist(接口和引脚说明)==
 
==Adapter Board Pinlist(接口和引脚说明)==
{| class="wikitable"
 
| colspan="3" |'''J8:Funcation Jumper(功能选择)'''
 
|-
 
|'''<big>Pin NO.(引脚号)</big>'''
 
|'''<big>NAME(名称)</big>'''
 
|'''<big>Remarks(说明)</big>'''
 
|-
 
|1
 
|CAM_VSYNC
 
|Internal Connect with J7-86 through a level shifter(3.3V to 1.8V)
 
|-
 
|2
 
|COM
 
|Internal pull up to 3.3V, Rpu=1.5KΩ
 
|-
 
|3
 
|Ext Trigger In
 
|Internal Connect with J9-1
 
|}
 
{| class="wikitable"
 
| colspan="3" |'''J9'''
 
|-
 
|'''<big>Pin NO.(引脚号)</big>'''
 
|'''<big>NAME(名称)</big>'''
 
|'''<big>Remarks(说明)</big>'''
 
|-
 
|1
 
|Ext Trigger In
 
|Internal Connect with J8-3
 
|-
 
|2
 
|GND
 
|
 
|-
 
|3
 
|NC
 
|
 
|}
 
{| class="wikitable"
 
| colspan="3" |'''J11'''
 
|-
 
|'''<big>Pin NO.(引脚号)</big>'''
 
|'''<big>NAME(名称)</big>'''
 
|'''<big>Remarks(说明)</big>'''
 
|-
 
|1
 
|12VIN
 
|DC12V INPUT(DC12V输入)
 
|-
 
|2
 
|GND
 
|
 
|}
 
{| class="wikitable"
 
| colspan="2" |'''J8,J9,SW1 Functional specifications(J8,J9,SW1功能说明)'''
 
|-
 
|'''<big>J8 Jumper Status(J8跳选状态)</big>'''
 
|'''<big>Remarks(说明)</big>'''
 
|-
 
|Short connection J8-1 and J8-2
 
(短接J8的1、2引脚)
 
|Select J7-86(CAM_VSYNC) as the trigger source,Only available Interconnect with TX2 platform
 
(与TX2/TX2平台主板互联时,此时选择的是J7-86(CAM_VSYNC)作为触发源)
 
|-
 
| rowspan="2" |Short connection J8-2 and J8-3
 
(短接J8的2、3引脚)
 
|Select J9-1(Ext Trigger In) as the trigger source
 
(此时选择的是J9-1(Ext Trigger In)作为外触发源)
 
|-
 
|SW1 is used for testing to simulate an external trigger signal,Internal Connect with J9-3
 
(此时SW1模拟一个外触发信号,与J9-3引脚连接在一起)
 
|}
 
 
{| class="wikitable"
 
{| class="wikitable"
 
| colspan="13" |'''J1 / J2 / J3 / J4 / J5 / J6'''
 
| colspan="13" |'''J1 / J2 / J3 / J4 / J5 / J6'''
Line 127: Line 45:
 
|-
 
|-
 
|<small>1</small>
 
|<small>1</small>
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>2</small>
 
|<small>2</small>
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>3</small>
 
|<small>3</small>
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>4</small>
 
|<small>4</small>
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>5</small>
 
|<small>5</small>
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>6</small>
 
|<small>6</small>
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>7</small>
 
|<small>7</small>
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>8</small>
 
|<small>8</small>
|<small>CSI_A_CLK_P</small>
 
 
|
 
|
|<small>CSI_B_CLK_P</small>
 
 
|
 
|
|<small>CSI_C_CLK_P</small>
 
 
|
 
|
|<small>CSI_D_CLK_P</small>
 
 
|
 
|
|<small>CSI_E_CLK_P</small>
 
 
|
 
|
|<small>CSI_F_CLK_P</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>9</small>
 
|<small>9</small>
|<small>CSI_A_CLK_N</small>
 
 
|
 
|
|<small>CSI_B_CLK_N</small>
 
 
|
 
|
|<small>CSI_C_CLK_N</small>
 
 
|
 
|
|<small>CSI_D_CLK_N</small>
 
 
|
 
|
|<small>CSI_E_CLK_N</small>
 
 
|
 
|
|<small>CSI_F_CLK_N</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>10</small>
 
|<small>10</small>
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>11</small>
 
|<small>11</small>
|<small>CSI_A_D1_P</small>
 
 
|
 
|
|<small>CSI_B_D1_P</small>
 
 
|
 
|
|<small>CSI_C_D1_P</small>
 
 
|
 
|
|<small>CSI_D_D1_P</small>
 
 
|
 
|
|<small>CSI_E_D1_P</small>
 
 
|
 
|
|<small>CSI_F_D1_P</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>12</small>
 
|<small>12</small>
|<small>CSI_A_D1_N</small>
 
 
|
 
|
|<small>CSI_B_D1_N</small>
 
 
|
 
|
|<small>CSI_C_D1_N</small>
 
 
|
 
|
|<small>CSI_D_D1_N</small>
 
 
|
 
|
|<small>CSI_E_D1_N</small>
 
 
|
 
|
|<small>CSI_F_D1_N</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>13</small>
 
|<small>13</small>
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>14</small>
 
|<small>14</small>
|<small>CSI_A_D0_P</small>
 
 
|
 
|
|<small>CSI_B_D0_P</small>
 
 
|
 
|
|<small>CSI_C_D0_P</small>
 
 
|
 
|
|<small>CSI_D_D0_P</small>
 
 
|
 
|
|<small>CSI_E_D0_P</small>
 
 
|
 
|
|<small>CSI_F_D0_P</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>15</small>
 
|<small>15</small>
|<small>CSI_A_D0_N</small>
 
 
|
 
|
|<small>CSI_B_D0_N</small>
 
 
|
 
|
|<small>CSI_C_D0_N</small>
 
 
|
 
|
|<small>CSI_D_D0_N</small>
 
 
|
 
|
|<small>CSI_E_D0_N</small>
 
 
|
 
|
|<small>CSI_F_D0_N</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>16</small>
 
|<small>16</small>
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>17</small>
 
|<small>17</small>
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
 
 
|
 
|
|<small>NC</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>18</small>
 
|<small>18</small>
|<small>RESERVE</small>
+
|
|<small>NC</small>
+
|
|<small>RESERVE</small>
+
|
|<small>NC</small>
+
|
|<small>RESERVE</small>
+
|
|<small>NC</small>
+
|
|<small>RESERVE</small>
+
|
|<small>NC</small>
+
|
|<small>RESERVE</small>
+
|
|<small>NC</small>
+
|
|<small>RESERVE</small>
+
|
|<small>NC</small>
+
|
 
|-
 
|-
 
|<small>19</small>
 
|<small>19</small>
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>20</small>
 
|<small>20</small>
|<small>SCL0</small>
+
|
|<small>3.3V Level</small>
+
|
|<small>SCL1</small>
+
|
|<small>3.3V Level</small>
+
|
|<small>SCL2</small>
+
|
|<small>3.3V Level</small>
+
|
|<small>SCL3</small>
+
|
|<small>3.3V Level</small>
+
|
|<small>SCL4</small>
+
|
|<small>3.3V Level</small>
+
|
|<small>SCL5</small>
+
|
|<small>3.3V Level</small>
+
|
 
|-
 
|-
 
|<small>21</small>
 
|<small>21</small>
|<small>SDA0</small>
+
|
|<small>3.3V Level</small>
+
|
|<small>SDA1</small>
+
|
|<small>3.3V Level</small>
+
|
|<small>SDA2</small>
+
|
|<small>3.3V Level</small>
+
|
|<small>SDA3</small>
+
|
|<small>3.3V Level</small>
+
|
|<small>SDA4</small>
+
|
|<small>3.3V Level</small>
+
|
|<small>SDA5</small>
+
|
|<small>3.3V Level</small>
+
|
 
|-
 
|-
 
|<small>22</small>
 
|<small>22</small>
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>23</small>
 
|<small>23</small>
|<small>Sync0</small>
 
 
|
 
|
|<small>Sync0</small>
 
 
|
 
|
|<small>Sync0</small>
 
 
|
 
|
|<small>Sync0</small>
 
 
|
 
|
|<small>Sync0</small>
 
 
|
 
|
|<small>Sync0</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>24</small>
 
|<small>24</small>
|<small>Sync1</small>
 
 
|
 
|
|<small>Sync1</small>
 
 
|
 
|
|<small>Sync1</small>
 
 
|
 
|
|<small>Sync1</small>
 
 
|
 
|
|<small>Sync1</small>
 
 
|
 
|
|<small>Sync1</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|-
 
|-
 
|<small>25</small>
 
|<small>25</small>
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
 
|-
 
|-
 
|<small>26</small>
 
|<small>26</small>
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
 
|-
 
|-
 
|<small>27</small>
 
|<small>27</small>
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
|<small>VDD_3V3_SLP</small>
+
|
|<small>PWR OUT</small>
+
|
 
|-
 
|-
 
|<small>28</small>
 
|<small>28</small>
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
 
 
|
 
|
|<small>GND</small>
+
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|-
 +
|<small>29</small>
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|-
 +
|<small>30</small>
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|
 
|
 
|
 
|}<br />
 
|}<br />
Line 926: Line 872:
  
 
==Adapter Board Dimension(板子尺寸)==
 
==Adapter Board Dimension(板子尺寸)==
[[File:ADP-N1-V2.0-CAD.jpg|alt=|none|thumb|800x800px|ADP-N1-V2.0 CAD / unit:mm]]
+
Download dwg file here
[[Media:ADP-N1-V2.0-DWG.dwg|Download dwg file here]]
 
 
== PCBA 3D STP File(PCBA 3D STP文件)==
 
== PCBA 3D STP File(PCBA 3D STP文件)==
[[Media:3D ADP-N1-V2.0.zip|download 3D STP file]]
+
download 3D STP file

Revision as of 17:38, 23 June 2022

Adapter Board:ADP-N4 Data Sheet

1 Product Introduction(产品介绍)

ADP-N4 is a camera interposer module for NVIDIA Jetson AGX Xavier、ORIN 、TX2 DevKit.

ADP-N1-V2.0是NVIDIA Jetson AGX Xavier、ORIN、TX2开发套件的摄像头转接模块。

2 Product Picture(产品图片)

PART NUMBER / 型号 FRONT VIEW / 正面图片 BACK VIEW / 背面图片
ADP-N4
ADP-N4
ADP-N4
ADP-N4
ADP-N4

3 Adapter Board Pinlist(接口和引脚说明)

J1 / J2 / J3 / J4 / J5 / J6
Pin NO. J1 J2 J3 J4 J5 J6
NAME Remarks NAME Remarks NAME Remarks NAME Remarks NAME Remarks NAME Remarks
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30


J7
Pin NO. NAME Remarks Pin NO. NAME Remarks Pin NO. NAME Remarks Pin NO. NAME Remarks
1 CSI_A_D0_P 31 CSI_C_D1_P 61 NC 91 NC
2 CSI_B_D0_P 32 CSI_D_D1_P 62 NC 92 NC
3 CSI_A_D0_N 33 CSI_C_D1_N 63 NC 93 NC
4 CSI_B_D0_N 34 CSI_D_D1_N 64 NC 94 NC
5 GND 35 GND 65 NC 95 NC
6 GND 36 GND 66 NC 96 NC
7 CSI_A_CLK_P 37 CSI_E_D0_P 67 NC 97 NC
8 CSI_B_CLK_P 38 CSI_F_D0_P 68 NC 98 NC
9 CSI_A_CLK_N 39 CSI_E_D0_N 69 GND 99 GND
10 CSI_B_CLK_N 40 CSI_F_D0_N 70 GND 100 GND
11 GND 41 GND 71 NC 101 NC
12 GND 42 GND 72 NC 102 NC
13 CSI_A_D1_P 43 CSI_E_CLK_P 73 NC 103 NC
14 CSI_B_D1_P 44 CSI_F_CLK_P 74 NC 104 NC
15 CSI_A_D1_N 45 CSI_E_CLK_N 75 CAM_I2C_SCL 1.8V Level 105 NC
16 CSI_B_D1_N 46 CSI_F_CLK_N 76 NC 106 NC
17 GND 47 GND 77 CAM_I2C_SDA 1.8V Level 107 NC
18 GND 48 GND 78 NC 108 VDD_3V3_SLP PWR
19 CSI_C_D0_P 49 CSI_E_D1_P 79 GND 109 VDD_5V0_IO_SYS PWR
20 CSI_D_D0_P 50 CSI_F_D1_P 80 GND 110 VDD_3V3_SLP PWR
21 CSI_C_D0_N 51 CSI_E_D1_N 81 NC 111 NC
22 CSI_D_D0_N 52 CSI_F_D1_N 82 NC 112 NC
23 GND 53 GND 83 NC 113 NC
24 GND 54 GND 84 VDD_3V3_SLP PWR 114 NC
25 CSI_C_CLK_P 55 NC 85 NC 115 GND
26 CSI_D_CLK_P 56 NC 86 CAM_VSYNC RESERVE 116 GND
27 CSI_C_CLK_N 57 NC 87 NC 117 NC
28 CSI_D_CLK_N 58 NC 88 NC 118 TX2 :VDD_5V0_IO_SYS AGX:VDD_3V3_IO_SYS PWR
29 GND 59 NC 89 NC 119 NC
30 GND 60 NC 90 NC 120 TX2 :VDD_5V0_IO_SYS AGX:VDD_3V3_IO_SYS PWR

4 Adapter Board Dimension(板子尺寸)

Download dwg file here

5 PCBA 3D STP File(PCBA 3D STP文件)

download 3D STP file