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Line 34: − + − + − + − + − + − |- − | colspan="2" |'''Device Functional Modes''' − |- − |Clocking Mode − |Synchronous Mode， FPD-Link III Clock reference derived from deserializer − |- − |Operating Mode − |CSI-2 Mode − |- − |Forward Channel Mode − |Synchronous Mode − |- − |Back Channel Mode − |Synchronous Mode − |- − |V-by-One HS Rate − |3.75Gbps（max） * 2（Link with V-by-One-HS-RX） Line 72:
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→Thechnical Detail (技术规格)
|-
|-
|Function
|Function
|Serializer
|MIPI® CSI-2 to V-by-One® HS conversion
|-
|-
|Input Compatibility
|Input Compatibility
|-
|-
|Output Compatibility
|Output Compatibility
|V-by-One HS
|V-by-One® HS standard version1.5
|-
|-
|'''Interface'''
|'''Interface'''
|-
|-
|MIPI INPUT
|MIPI INPUT
|MIPI CSI-2 4lane (800Mbsp/lane max), J1 / J2
|MIPI CSI-2，Supports up to 1.5Gbps/lane，Supports 2 or 4 lanes
|-
|-
|MIPI INPUT Connector
|MIPI INPUT Connector
|FFC socket（J1 / J2）
|FFC socket（J1 / J2）
|-
|-
|LVDS OUTPUT
|V-by-One® HS OUTPUT
|V-by-One HS (3.75Gbps data rate * 2)
|V-by-One HS，Supports up to 4.0Gbps（effective rate 3.2Gbps），Supports 1 or 2 lanes
|-
|-
|LVDS OUTPUT Connector
|V-by-One® HS OUTPUT Connector
|FAKRA Z Compatibility ( J3 / J6)
|FAKRA Z Compatibility ( J3 / J6)
|-
|-
|MPIO
|GPIO
|2 output，1 input
|2 output，1 input
|-
|-
| colspan="2" |'''General'''
| colspan="2" |'''General'''
|-
|-
|POC DC Power Input
|POC DC Power Input
|DC 9-15V （J2）
|DC 9-15V （Only J2 is powered by POC）
|-
|-
|Dimension
|Dimension