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{| class="wikitable"
{| class="wikitable"
| colspan="17" rowspan="2" |时序图
| colspan="17" |'''LVDS TIMING'''
|-
|-
|-
|'''LVDS BUS'''
| colspan="2" |'''Dn-1'''
| colspan="2" |N-1
| colspan="7" |'''Dn'''
| colspan="7" |N
| colspan="5" |'''Dn+1'''
| colspan="5" |N+1
|
|
|'''Parallel Data'''
|并行BUS
|-
|-
|CLK
|CLK
|…
|…
|<--C[0:6]
|<--C[0:6]
|}
{| class="wikitable"
| colspan="17" |'''YUV TIMING'''
|-
|-
| colspan="17" rowspan="2" |YUV数据装载图
|'''LVDS BUS'''
| colspan="2" |'''Dn-1'''
| colspan="7" |'''Dn'''
| colspan="5" |'''Dn+1'''
| colspan="2" |N-1
|
| colspan="7" |N
|'''YUV Parallel Data'''
| colspan="5" |N+1
|
|YUV数据
|-
|-
|CLK
|CLK
|}
|}
{| class="wikitable"
{| class="wikitable"
| rowspan="2" |lane号
|'''Lane NO.'''
| rowspan="2" |接口
|'''Interface'''
| rowspan="2" |YUV数据
|'''YUV Data'''
| rowspan="2" |Xilinx SelectIO并行输出
|'''Xilinx SelectIO Parallel Data Output'''
|-
|-
| rowspan="7" |L0
| rowspan="7" |'''L0'''
|A6
|A6
|UNUSE
|UNUSE
|lvds_data_out[0]
|lvds_data_out[0]
|-
|-
| rowspan="7" |L1
| rowspan="7" |'''L1'''
|B6
|B6
|Y3
|Y3
|lvds_data_out[1]
|lvds_data_out[1]
|-
|-
| rowspan="7" |L2
| rowspan="7" |'''L2'''
|C6
|C6
|UV2
|UV2