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Line 168: − |'''Xilinx SelectIO Parallel Data Output''' − |lvds_data_out[18] − |lvds_data_out[15] − |lvds_data_out[12] − |lvds_data_out[9] − |lvds_data_out[6] − |lvds_data_out[3] − |lvds_data_out[0] − |lvds_data_out[19] − |lvds_data_out[16] − |lvds_data_out[13] − |lvds_data_out[10] − |lvds_data_out[7] − |lvds_data_out[4] − |lvds_data_out[1] − |lvds_data_out[20] − |lvds_data_out[17] − |lvds_data_out[14] − |lvds_data_out[11] − |lvds_data_out[8] − |lvds_data_out[5] − |lvds_data_out[2]
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== LVDS时序和数据格式 LVDS Timing and Data Formart ==
{| class="wikitable"
{| class="wikitable"
| colspan="17" |'''LVDS TIMING'''
| colspan="17" |'''LVDS TIMING'''
|'''Interface'''
|'''Interface'''
|'''YUV Data'''
|'''YUV Data'''
|-
|-
| rowspan="7" |'''L0'''
| rowspan="7" |'''L0'''
|A6
|A6
|UNUSE
|UNUSE
|-
|-
|A5
|A5
|UNUSE
|UNUSE
|-
|-
|A4
|A4
|LV
|LV
|-
|-
|A3
|A3
|FV
|FV
|-
|-
|A2
|A2
|Y0
|Y0
|-
|-
|A1
|A1
|Y1
|Y1
|-
|-
|A0
|A0
|Y2
|Y2
|-
|-
| rowspan="7" |'''L1'''
| rowspan="7" |'''L1'''
|B6
|B6
|Y3
|Y3
|-
|-
|B5
|B5
|Y4
|Y4
|-
|-
|B4
|B4
|Y5
|Y5
|-
|-
|B3
|B3
|Y6
|Y6
|-
|-
|B2
|B2
|Y7
|Y7
|-
|-
|B1
|B1
|UV0
|UV0
|-
|-
|B0
|B0
|UV1
|UV1
|-
|-
| rowspan="7" |'''L2'''
| rowspan="7" |'''L2'''
|C6
|C6
|UV2
|UV2
|-
|-
|C5
|C5
|UV3
|UV3
|-
|-
|C4
|C4
|UV4
|UV4
|-
|-
|C3
|C3
|UV5
|UV5
|-
|-
|C2
|C2
|UV6
|UV6
|-
|-
|C1
|C1
|UV7
|UV7
|-
|-
|C0
|C0
|DE
|DE
|}
|}